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1 ltc1411 single supply 14-bit 2.5msps adc february 2001 the ltc ? 1411 is a 2.5msps sampling 14-bit a/d con- verter in a 36-pin ssop package, which typically dissi- pates only 195mw from a single 5v supply. this device comes complete with a high bandwidth sample-and- hold, a precision reference, a programmable gain ampli- fier and an internally trimmed clock. the adc can be powered down with either the nap or sleep mode for low power applications. the ltc1411 converts either differential or single-ended inputs and presents data in 2s complement format. maxi- mum dc specs include 2lsb inl, 14 bits no missing code and an internal reference with 15ppm/ c drift, over temperature. outstanding dynamic performance includes 80dbs/(n + d) and 88db thd. the ltc1411 has four levels of programmable gain (0db, C 3db, C 6db and C 9db) selected by two digital input pins, pga0 and pga1. this provides input spans of 1.8v, 1.27v, 0.9v and 0.64v. an out-of-the-range signal together with the d13 (msb) will indicate whether a signal is over or under the adcs input range. a simple conver- sion start input and a data ready signal ease connections to fifos, dsps and microprocessors. n sample rate: 2.5msps n 80db s/(n + d) and 88db thd n single 5v operation n no pipeline delay n onboard programmable gain amplifier n low power dissipation: 195mw (typ) n true differential inputs reject common mode noise n out-of-range indicator n internal or external reference n sleep (1 m a) and nap (2ma) shutdown modes n 36-pin ssop package , ltc and lt are registered trademarks of linear technology corporation. n telecommunications n high speed data acquisition n digital signal processing n multiplexed data acquisition systems n spectrum analysis n imaging systems final electrical specifications information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. otr d13 ognd dvp ov dd control logic 2.5v bandgap reference internal clock 14-bit adc output drivers refout 14 + pga0 pga1 convst dgnd 1411 bd a in + a in nap slp avm 7, 8, 9 3 refin 2k 5k 5k 2 1 32 33 34 35 36 11 agnd 31 26 busy 27 d0 25 12 28 29 30 4 refcom1 5 refcom2 6 x1.62/ x1.15 avp 10 features descriptio u applicatio s u block diagra w
2 ltc1411 avp = dvp = ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 6v analog input voltage (note 3) ... C 0.3v to (v dd + 0.3v) digital input voltage (note 4) .................. C 0.3v to 10v digital output voltage ............... C 0.3v to (v dd + 0.3v) power dissipation .............................................. 500mw operating temperature range ltc1411c ............................................... 0 c to 70 c ltc1411i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ltc1411cg ltc1411ig 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 slp nap pga0 pga1 convst dgnd dvp ov dd ognd busy otr d0 d1 d2 d3 d4 d5 d6 a in + a in refout refin refcom1 refcom2 agnd1 agnd2 agnd3 avp avm d13 (msb) d12 d11 d10 d9 d8 d7 t jmax = 125 c, q ja = 95 c/ w temperature range, otherwise specifications are t a = 25 c. (notes 5, 6) the l denotes specifications which apply over the full operating parameter conditions min typ max units resolution (no missing codes) l 14 bits integral linearity error (note 7) l 2 lsb offset error (note 8) 16 lsb l 24 lsb full-scale error external reference = 2.5v 60 lsb full-scale tempco i out(ref) = 0 15 ppm/ c accuracy ic dy u w a t a = 25 c (note 5) symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 500khz input signal 80 db thd total harmonic distortion 500khz input signal, up to 5th harmonic C 88 db peak harmonic or spurious noise 500khz input signal 88 db imd intermodulation distortion f in1 = 97.7khz, f in2 = 104.2khz C 86 db full power bandwidth 40 mhz full linear bandwidth s/(n + d) 3 76db 1.0 mhz transition noise 0.66 lsb rms absolute axi u rati gs w ww u package/order i for atio uu w co verter characteristics u consult factory for parts specified with wider operating temperature ranges.
3 ltc1411 symbol parameter conditions min typ max units v in analog input range (note 9) (a in + ) C (a in C ), pga0 = pga1 = 5v 1.8 v (a in + ) C (a in C ), pga0 = 5v, pga1 = 0v 1.27 v (a in + ) C (a in C ), pga0 = 0v, pga1 = 5v 0.9 v (a in + ) C (a in C ), pga0 = pga1 = 0v 0.64 v common mode input range a in + or a in C 0v dd v c in analog input capacitance between conversions (sample mode) 10 pf during conversions (hold mode) 4 pf t acq sample-and-hold acquisition time 100 ns t ap sample-and-hold aperture delay time C 0.5 ns t jitter sample-and-hold aperture delay time jitter 1 ps rms cmrr analog input common mode rejection ratio 0v < (a in C = a in + ) < v dd 63 db parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.01 lsb/ v v ref load regulation 0 ? i out ? 1ma 2 lsb refcom2 output voltage i out = 0, pga0 = pga1 = 5v 4.05 v digital i puts a n d outputs u u symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd , except slp, nap (note 11) l 10 m a c in digital input capacitance 2pf v oh high level output voltage v dd = 4.75v, i o = C 10 m a 4.75 v v dd = 4.75v, i o = C 200 m a l 4.0 v v ol low level output voltage v dd = 4.75v, i o = 160 m a 0.05 v v dd = 4.75v, i o = 1.6ma l 0.10 0.4 v i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma power require e ts w u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 5) symbol parameter conditions min typ max units v dd supply voltage (note 9) 4.75 5.25 v i dd supply current l 39 65 ma nap mode nap = 0v 2 ma sleep mode slp = 0v 1 m a p d power dissipation l 195 325 mw nap mode nap = 0v 10 mw sleep mode slp = 0v 5 m w the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 5) t a = 25 c (note 5) put u i a a u log i ter al refere ce characteristics uu u t a = 25 c (note 5)
4 ltc1411 ti i g characteristics w u range, otherwise specifications are t a = 25 c. (notes 5) (see figures 4, 6) the l denotes specifications which apply over the full operating temperature symbol parameter conditions min typ max units f sample(max) maximum sampling frequency (note 9) l 2.5 mhz t conv conversion time l 250 350 ns t acq acquisition time 100 ns t 0 slp - to convst wake-up time 10 m f bypass capacitor at refcom2 pin 10 ms t 1 nap - to convst wake-up time 200 ns t 2 convst low time (note 10) l 20 ns t 3 convst to busy delay c l = 50pf 5 ns t 4 data ready after busy - 20 ns t 5 convst high time (note 10) l 20 ns t 6 aperture delay of sample-and-hold C 0.5 ns note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd, ognd, avm and agnd wired together unless otherwise noted. note 3: when these pin voltages are taken below agnd or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma without latchup. note 4: when these pin voltages are taken below agnd, they will be clamped by internal diodes. this product can handle input currents greater than 100ma below agnd without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 2.5mhz at 25 c and t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a single- ended a in + input with a in C tied to an external 2.5v reference voltage. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. note 9: recommended operating conditions. note 10: the falling convst edge starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for best performance ensure that convst returns high within 20ns after conversion start of after busy rises. note 11: slp and nap have an internal pull-down so the pins will draw approximately 7 m a when tied high and less than 1 m a when tied low. a in + (pin 1): positive analog input. the adc converts the difference voltage between a in + and a in C with program- mable input ranges of 1.8v, 1.27v, 0.9v and 0.64v depending on pga selection. a in + has common mode range between 0v and v dd . a in C (pin 2): negative analog input. this pin can be tied to the refout pin of the adc or tied to an external dc voltage. this voltage is also the bipolar zero for the adc. a in C has common mode range between 0v and v dd . refout (pin 3): 2.5v reference output. bypass to agnd1 with a 22 m f tantalum capacitor if refout is tied to a in C . no capacitor is needed if the external reference is used to drive a in C . refin (pin 4): reference buffer input. this pin can be tied to refout or to an external reference if more precision is required. refcom1 (pin 5): noise reduction pin. put a 10 m f bypass capacitor at this pin to reduce the noise going into the reference buffer. refcom2 (pin 6): 4.05v reference compensation pin. bypass to agnd1 with a 10 m f tantalum capacitor in parallel with a 0.1 m f ceramic. agnd (pins 7 to 9): analog ground. agnd1 is the ground for the reference. agnd2 is the ground for the comparator and agnd3 is the ground for the remaining analog circuitry. uu u pi fu ctio s
5 ltc1411 dgnd (pin 31): digital ground. convst (pin 32): conversion start signal. this active low signal starts a conversion on its falling edge. pga1, pga0 (pins 33, 34): programmable gain logic inputs. this adc has four levels of gain controlled by these two pins. for the logic inputs applied to pga0 and pga1, the following summarizes the gain levels and the analog input range with a in C tied to 2.5v. table 1. input spans for ltc1411 input refcom2 pga0 pga1 level span voltage 5v 5v 0db 1.8v 4v 5v 0v C 3db 1.28v 2.9v 0v 5v C 6db 0.9v 2v 0v 0v C 9db 0.64v 1.45v nap (pin 35): nap input. driving this pin low will put the adc in the nap mode and will reduce the supply current to 2ma. slp (pin 36): sleep input. driving this pin low will put the adc in the sleep mode and the adc draws less than 1 m a of supply current. otr 5v or 3v d13 ognd ov dd control logic 2.5v bandgap reference internal clock 14-bit adc output drivers refout 14 + pga0 pga1 convst dgnd 1411 ta01 a in + a in nap slp + avm 7, 8, 9 3 refin 22 f* 10 f 10 f 2k 5k 5k 2 1 32 33 34 35 36 11 agnd *a 22 f capacitor is needed if refout is used to drive a in 31 26 busy 27 d0 25 12 28 29 4 refcom1 5 refcom2 6 + 30 10 + + + x1.62/ x1.15 uu u w typical co ectio diagra uu u pi fu ctio s avp (pin 10): 5v analog power supply. bypass to agnd with a 10 m f tantalum capacitor. avm (pin 11): analog and digital substrate pin. tie this pin to agnd. d13 to d0 (pins 12 to 25): digital data outputs. d13 is the msb (most significant bit). otr (pin 26): out-of-the-range pin. this pin can be used in conjunction with d13 to determine if a signal is less than or greater than the analog input range. if d13 is low and otr is high, the analog input to the adc exceeds the maximum voltage of the input range. busy (pin 27): busy output. converter status pin. it is low during conversion. ognd (pin 28): digital ground for output drivers (data bits, otr and busy). ov dd (pin 29): 3v or 5v digital power supply for output drivers (data bits, otr and busy). bypass to ognd with a 10 m f tantalum capacitor. dvp (pin 30): 5v digital power supply pin. bypass to ognd with a 10 m f tantalum capacitor.
6 ltc1411 the full reference voltage of 4v. the analog input range is 0.7v to 4.3v with a in C = 2.5v. this corresponds to an input span of 1.8v with respect to the voltage applied to a in C . for the C 3db setting the internal reference is reduced to 0.707 ? 4v = 2.9v. likewise the input span is reduced to 1.28v. the following table lists the input span with respect to a in C for the different pga0 and pga1 settings. table 1. input spans for ltc1411 input refcom2 pga0 pga1 level span voltage 5v 5v 0db 1.8v 4v 5v 0v C 3db 1.28v 2.9v 0v 5v C 6db 0.9v 2v 0v 0v C 9db 0.64v 1.45v when changing from one input span to another, more time is needed for the refcom2 pin to reach the correct level because the bypass capacitor on the pin needs to be charged or discharged. figure 2 shows the recommended capacitors at the refcom1 and refcom2 pins (10 m f each). when C 6db or C 9db is selected, the voltage at refcom1 (see figure 2) must first settle before refcom2 reaches the correct level. the typical delay is about 600ms. when the refcom2 level is changed from 2.9v to 4v (changing pga setting from C 3db to 0db), the typical delay is 3ms. however, if the voltage at refcom2 is changed from 4v to 2.9v (changing pga setting from 0db to C 3db) only a 60 m a sink current is present to discharge the 10 m f bypass capacitor. in this case a pull-down resistor, for example of 5k, at refcom2 will typically reduce the delay from 400ms to 100ms. internal reference the ltc1411 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500v. if this refout pin is used to drive the a in C pin, a 22 m f tantalum bypass capacitor is required and this refout voltage sets the bipolar zero for the adc. the refin pin is connected to the reference buffer through a 2k resistor and two pga switches. the refin pin can be driving the analog input the differential analog inputs of the ltc1411 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the a in C input is tied to a fixed dc voltage such as the refout pin of the ltc1411 or an external source). figure 1 shows a simplified block diagram for the analog inputs of the ltc1411. the a in + and a in C are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charg- ing the sample-and-hold capacitors at the end of conver- sion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuits is low, then the ltc1411 inputs can be driven directly. more acquisition time should be allowed for a higher impedance source. onboard programmable gain amplifier the ltc1411 has two logic input pins (pga0 and pga1) that are used to select one of four analog input ranges. these input ranges are set by changing the reference voltage that is applied to the internal dac of the adc (refcom2). for the 0db setting the internal dac sees + comp a in + c smpl hold sample a in c smpl +c dac +v dac ? dac ? dac hold hold sample hold sar output latches 14 d13 d0 1411 f01 zeroing switches figure 1. simplified block diagram applicatio s i for atio wu uu
7 ltc1411 refcom2 10 f 1411 f02 refcom1 refin* refout 10 f this pin can be tied to refout or an external source a 22 f capacitor is needed if refout is used to drive a in * ** 22 f** 2k 5k 5k 2.5v bandgap reference x1.62 figure 2. reference structure for the ltc1411 for pga1 = pga0 = 5v figure 3 shows a typical reference, the lt1019a-2.5 connected to the ltc1411. this will provide an improved drift (equal to the maximum 5ppm/ c of the lt1019a-2.5). digital interface the adc has a very simple digital interface with only one control input, convst. a logic low applied to the convst input will initiate a conversion. the adc presents digital data in 2s complement format with bipolar zero set by the voltage applied to the a in C pin. internal clock the internal clock is factory trimmed to achieve a typical conversion time of 260ns. with the typical acquisition time of 100ns, a throughput sampling rate of 2.5msps is guaranteed. out-of-the-range signal (otr) the ltc1411 has a digital output, otr, that indicates if an analog input signal is out of range. the otr remains low when the analog input is within the specified range. once the analog signal goes to the most negative input (10 0000 0000 0000) or 64lsb above the specified most positive input, otr will go high. by noring d13 (msb) and its complement with otr, overrange and underrange can be detected as shown in figure 4. table 2 is the truth table of the out-of-the-range circuit in figure 4. 3 2 6 4 1 2 4 7, 8, 9 input range: 0.7v to 4.3v 10 f 1411 f03 lt1019a-2.5 v in gnd v out 5v 5v ltc411 a in + a in agnd refin figure 3. supplying a 2.5v reference voltage to the ltc1411 with the lt1019a-2.5 otr d13 d13 ??for overrange u1-a u1-b u1-a, u1-b = 74hc or equivalent ??for underrange 1411 f04 figure 4. overrange and underrange logic table 2. out-of-the-range truth table otr d13 (msb) analog input 0 0 in range 0 1 in range 1 0 overrange 1 1 underrange connected to refout directly or to an external reference. figure 2 shows the reference and buffer structure for the ltc1411. the input to the reference buffer is either refin or 1/2 of refin depending on the pga selection. the refcom1 pin bypassed with a 10 m f tantalum capacitor helps reduce the noise going into the buffer. the reference buffer has a gain of 1.62 or 1.15 (depends on pga selection). it is compensated at the refcom2 pin with a 10 m f tantalum capacitor. the input span of the adc is set by the output voltage of this refcom2 voltage. for a 2.5v input at the refin pin, the refcom2 will have 4v output for pga1 = pga0 = 5v and the adc will have a span of 3.6v. applicatio s i for atio wu uu
8 ltc1411 power shutdown (sleep and nap modes) the ltc1411 provides two shutdown features that will save power when the adc is inactive. by driving the slp pin low for sleep mode, the adc shuts down to less than 1 m a. after release from the sleep mode, the adc needs 10ms (10 m f bypass capacitor on the refcom2 pin) to wake up. in nap mode, all the power is off except the internal refer- ence which is still active for the other external circuitry. in this mode the adc draws about 2ma instead of 39ma (for minimum power, the logic inputs must be within 600mv from the supply rails). the wake-up time from nap mode to active state is 200ns as shown in figure 5. figure 5. nap to convst wake-up timing t 1 nap convst 1411 f05 board layout and bypassing wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the ltc1411, a printed circuit board with a ground plane is required. layout for the printed circuit board should ensure that the digital and analog signal lines are separated as much as possible. in particu- lar, care should be taken not to run any digital track alongside an analog signal track. an analog ground plane separate from the logic system ground should be established under and around the adc. agnd1, 2, 3 (pins 7 to 9), avm (pin 11), dgnd (pin 31) and ognd (pin 28) and all other analog grounds should be connected to a single analog ground point. the refout, refcom1, refcom2 and avp should bypass to this analog ground plane (see figure 6). no other digital grounds should be connected to this analog ground plane. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. 1411 f06 a in + refcom2 ov dd dvp avp ltc1411 digital system analog input circuitry refcom1 5 2 6 29 31 ognd dgnd 28 avm 11 10 30 1 refin 4 refout 3 a in agnd1 7 agnd2 8 + agnd3 9 figure 6. power supply grounding practice applicatio s i for atio wu uu
9 ltc1411 timing and control conversion start is controlled by the convst digital input. the falling edge transition of the convst will start a conversion. once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. figure 7b convst starts a conversion with a short active high pulse figure 7a. convst starts a conversion with a short active low pulse data n db13 to db0 data (n + 1) db13 to db0 data (n ?1) db13 to db0 convst busy 1411 f7a t 2 t conv t 3 t acq t 4 data (sample n) data (n ?1) db13 to db0 (sample n) convst busy 1411 f07b t conv t 3 t 5 t 4 data n db13 to db0 data (n + 1) db13 to db0 data t 3 t 5 t acq the digital output code is updated at the end of conversion about 5ns after busy rises, i.e., output data is not valid on the rising edge of busy. valid data can be latched with the falling edge of busy or with the rising edge of convst. in either case, the data latched will be for the previous conversion results. figures 7a and 7b are the timing diagrams for the ltc1411. applicatio s i for atio wu uu
10 ltc1411 figure 8 is the input/output characteristics of the adc when a in C = 2.5v. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, figure 8. ltc1411 bipolar transfer characteristics (2s complement) input voltage (v) 2.5v output code ? lsb 1411 f08 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 ?1lsb fs/2 1lsb = = = 219.7 v 3.6v 16384 fs 16384 1.5lsb, 2.5lsb... fs C 1.5lsb). the output code is scaled such that 1lsb = fs/16384 = 3.6v/16384 = 219.7 m v. applicatio s i for atio wu uu
11 ltc1411 dimensions in inches (millimeters) unless otherwise noted. g package 36-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) u package descriptio g36 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.67 ?12.93* (0.499 ?0.509) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * **
12 ltc1411 ? linear technology corporation 2001 1411i lt/tp 0201 2k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com related parts part number resolution speed comments 16-bit ltc1608 16 500ksps 2.5v input range, pin compatible with ltc1604 ltc1604 16 333ksps 2.5v input range, 5v supply ltc1606 16 250ksps 10v input range, pin compatible with ltc1605 ltc1609 16 200ksps serial interface ltc1605/-1/-2 16 100ksps 10v/ 4v/0v to 4v input ranges, single 5v supply 14-bit ltc1414 14 2.2msps 150mw, 81db sinad and 95db sfdr ltc1419 14 800ksps 150mw, 81.5db sinad and 95db sfdr ltc1416 14 400ksps 75mw, low power with excellent ac specs ltc1417 14 400ksps 20mw, serial interface, 16-lead ssop package ltc1418 14 200ksps 15mw, single 5v, serial/parallel i/o 12-bit ltc1420 12 10msps 5v or 5v supply, 71db sinad and input pga ltc1412 12 3msps 150mw, 71db sinad and 84db thd ltc1402 12 2.2msps 90mw, serial interface, 16-lead ssop package ltc1410 12 1.25msps 150mw, 71.5db sinad and 84db thd ltc1415 12 1.25msps 55mw, single 5v supply ltc1409 12 800ksps 80mw, 71.5db sinad and 84db thd ltc1279 12 600ksps 60mw, single 5v or 5v supply ltc1404 12 600ksps high speed serial i/o in so-8 package ltc1278-5 12 500ksps 75mw, single 5v or 5v supply ltc1278-4 12 400ksps 75mw, single 5v or 5v supply ltc1400 12 400ksps high speed serial i/o in so-8 package ltc1405 12 5ksps 5v or 5v supply, input pga, pin compatible with ltc1420

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